Integrated circuits (IC's) and other semiconductor devices are extremely sensitive to the high voltages that may be generated by contact with an ESD event. As such, electrostatic discharge (ESD) protection circuitry is essential for integrated circuits. An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) and leads to pulses of high current (several amperes) of a short duration (typically, 100 nanoseconds). An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. During installation of integrated circuits into products, these electrostatic discharges may destroy the IC's and thus require expensive repairs on the products, which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may have been subjected.
The ESD problem has been especially pronounced in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) field effect technologies, which require new considerations and approaches for ESD protection. An SOI technique involves embedding an insulation layer, such as silicon dioxide (SiO2), having a thickness of approximately 100-400 nanometers (nm) between a semiconductor device region (e.g., active region of a transistor) and the substrate.
However, the thermal properties of the extremely thin active silicon film layer are poor in terms of thermal conductivity. Specifically, silicon dioxide (SiO2) has a very poor thermal conductivity compared to silicon. As a consequence, the active device region is thermally isolated from the substrate disposed below the insulating layer. Therefore, when an ESD event occurs, heat generated at the ESD device (e.g., an SCR) can not be dissipated by the substrate. Accordingly, during an ESD event, an active area of the ESD device is subject to excessive heat, which may cause damage to the ESD device.
Furthermore low voltage ESD current conduction is also required in order to protect very thin gate oxides. Such thin gate oxides typically have a thickness of 0.8 to 2.4 nanometers, and are typically used in advanced SOI processes, since SOI has significant advantages for high speed IC applications. In addition to providing ESD protection for the very thin gate oxides, it is also desirable that the trigger voltage be very low and that any trigger overshoot is limited as much as possible. Therefore, there is a need in the art to limit power dissipation across the active region of an SOI ESD protection device, as well as providing very fast triggering capabilities for the SOI protection device during an ESD event.